One process for forming contact regions in metal oxide semiconductor (MOS) devices is the self-aligned silicide (salicide) technique. A metal film is deposited over a MOS structure under processing conditions that result in the reaction of the metal with exposed silicon areas of the source and drain regions and of the polysilicon gate element to form low resistance metal silicide contact regions. An exemplary salicide process is outlined in Published U.S. patent application No. 2002/0019119 to Saigal et al., the entirety of which is hereby incorporated by reference herein.
As polysilicon gate line widths decrease toward 0.07 μm and below, silicide agglomeration begins to limit the salicide process capabilities, particularly with respect to N+ polysilicon gates. Specifically, the narrow line width effect causes an increase in the effective sheet resistance of the gate contact element and introduces difficulties in the fabrication process.
U.S. Pat. No. 6,326,290 to Chiu, issued Dec. 4, 2001, proposes two alternate gate electrode structures with expanded top portions, one generally having a T shaped polysilicon gate element and one generally having a Y shaped polysilicon gate element. While the expanded poly gate electrode structures reduce electrode effective sheet resistance, there still remains a need for a new method of forming such structures that utilizes popular damascene process techniques. Still further, alternative expanded structures and methods of forming the same are needed to provide added design flexibility for sub micron device architectures.